NXP Semiconductors /MIMXRT1052 /SEMC /INTR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as INTR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (IPCMDDONE)IPCMDDONE 0 (IPCMDERR)IPCMDERR 0 (AXICMDERR)AXICMDERR 0 (AXIBUSERR)AXIBUSERR 0 (NDPAGEEND)NDPAGEEND 0 (NDNOPEND)NDNOPEND

Description

Interrupt Enable Register

Fields

IPCMDDONE

IP command normal done interrupt

IPCMDERR

IP command error done interrupt

AXICMDERR

AXI command error interrupt

AXIBUSERR

AXI bus error interrupt

NDPAGEEND

This interrupt is generated when the last address of one page in NAND device is written by AXI command

NDNOPEND

This interrupt is generated when all pending AXI write command to NAND is finished on NAND interface.

Links

() ()